In the ensuing description of the prior art and the present invention, the following are herein incorporated by reference:
"Enterprise Systems Architecture/390 Principles of Operation," Order No. SA22-7201-02, available through IBM branch offices, 1994; PA1 "IEEE standard for binary floating-point arithmetic, ANSI/IEEE Std 754-1985," The Institute of Electrical and Electronic Engineers, Inc., New York, August 1985; and
Commonly assigned U.S. patent application Ser. No. 08/414,250 to Eric Mark Schwarz, et al., filed Mar. 31, 1995, now issued U.S. Pat. No. 5,687,106, and entitled "Implementation of Binary Floating Point Using Hexadecimal Floating Point Unit".
Previous hardware implementations of floating-point arithmetic have provided various radixes, including binary, decimal, or hexadecimal. But only a single radix was supported in any particular implementation. As future machines are built, they must be compatible with previous machines, and must also provide support for new formats. A new requirement emerges to provide hardware support for more than one format. For example, there is a requirement to support both the IBM System/360 hexadecimal and the IEEE binary floating-point formats.
Providing a computer with both modes permits more flexibility in handling applications, and permits a smoother transition between old applications and data using one mode and new applications and data in the new mode. Several approaches to providing support for two floating-point formats can be considered. One approach would be to provide separate registers and instructions for each format. This approach would keep the problems of complexity and interaction between the two modes to a minimum, but it does not provide for the synergistic effects of an integrated solution.
In the hereinabove cited, commonly assigned U.S. Patent Application to Schwarz et al., a computer system is described, including a floating point processor unit, in which the same instructions and registers are used for two floating point formats, along with a mode to control which format is to be used. The two modes specifically described therein are the IBM S/390 hexadecimal floating-point (HFP) mode and the IEEE 754 binary floating-point (BFP) modes. The concept of mode independent code reduces the problems associated with compiler support of both modes and also permits program modules to be written which cart be called in both modes. However, this also present several unique problems which must be solved.
For example, it may be appreciated that there will be applications which must operate on data in both types of formats and will also require conversions of data between the two modes. Also, it may be appreciated that in the mixed environment, it will be necessary to provide math libraries for both modes. In some cases, the exact sequence of code for the two modes will of necessity be different, but in other cases it may be possible and desirable to provide program modules which can operate in either mode.
It is recognized, therefore, that a computer system that provides multiple floating point modes presents unique problems in order to provide for mode-independent applications, and thus requires instructions for implementing operations to support veritable mode independent operation.